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YI Memory Map

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Regs Address Length Type Description Details
$420D 1 byte SNES Register (Hardware) wb++++ MEMSEL - ROM Access Speed -------f f = FastROM select. The SNES uses a master clock running at about 21.477 MHz (current theory is 1.89e9/88 Hz). By default, the SNES takes 8 master cycles for each ROM access. If this bit is set and ROM is accessed via banks $80-$FF, only 6 master cycles will be used. This register is initialized to $00 on power on (or reset?). See my memory map and timing doc (memmap.txt) for more details. Memory Map and Timings
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