YI Memory Map
Misc.
ASM
Super FX
Object Palette
Sprite Palette
Layer 1 Tilemap
Layer 2 Tilemap
Layer 3 Tilemap
Layer 4 Tilemap
Sprite Tilemap
Player Tilemap
Misc. Tilemap
Player Physics
Level Data
Pointer
Music
Sprite Number
Debug
Sound Effect
Timer
Empty
Subroutine
Coordinate
Level Number
Map
Cutscene
Controller
Sprite Physics
Bandit Mini-Game
Bonus Challenge
Boss
Pause Screen
Text
Misc.
ASM
Super FX
Object Palette
Sprite Palette
Layer 1 Tilemap
Layer 2 Tilemap
Layer 3 Tilemap
Layer 4 Tilemap
Sprite Tilemap
Player Tilemap
Misc. Tilemap
Player Physics
Level Data
Pointer
Music
Sprite Number
Debug
Sound Effect
Sprite Table
Timer
Empty
Subroutine Coordinate
Level Number
Map
Cutscene
Controller
Sprite Physics
Bandit Mini-Game
Flag
Bonus Challenge
Boss
Pause Screen
Text
Misc.
ASM
Super FX
Object Palette
Sprite Palette
Layer 1 Tilemap
Layer 2 Tilemap
Layer 3 Tilemap
Layer 4 Tilemap
Sprite Tilemap
Player Tilemap
Misc. Tilemap
Player Physics
Level Data
Pointer
Music
Sprite Number
Debug
Sound Effect
Timer
Empty
Subroutine
Coordinate
Level Number
Map
Cutscene
Controller
Sprite Physics
Bandit Mini-Game
Bonus Challenge
Boss
Pause Screen
Text
Table
Graphics
SNES Register (PPU)
SNES Register (APU)
SNES Register (Hardware)
SNES Register (Controller)
SNES Register (DMA)
Super FX Register
Misc.
ASM
Super FX
Object Palette
Sprite Palette
Layer 1 Tilemap
Layer 2 Tilemap
Layer 3 Tilemap
Layer 4 Tilemap
Sprite Tilemap
Player Tilemap
Misc. Tilemap
Player Physics
Level Data
Pointer
Music
Sprite Number
Debug
Sound Effect
Timer
Empty
Subroutine
Coordinate
Level Number
Map
Cutscene
Controller
Sprite Physics
Bandit Mini-Game
Bonus Challenge
Boss
Pause Screen
Text
Table
Graphics
Regs Address
Length
Type
Description
Details
$420D
1 byte
SNES Register (Hardware)
w b + + + + MEMSEL - ROM Access Speed
-------f
f = FastROM select. The SNES uses a master clock running at
about 21.477 MHz (current theory is 1.89e9/88 Hz). By default, the
SNES takes 8 master cycles for each ROM access. If this bit is set
and ROM is accessed via banks $80-$FF, only 6 master cycles will be
used.
This register is initialized to $00 on power on (or reset?).
See my memory map and timing doc (memmap.txt) for more details.
Memory Map and Timings