r b++++ TIMEUP - IRQ Flag
i-------
i = IRQ Flag. This bit is set just after an IRQ fires (at the
moment, it seems to have the same delay as the NMI Flag of $4210
has following NMI), and is cleared on read or write. Supposedly, it
is required that this register be read during the IRQ handler. If
this really is the case, then I suspect that that read is what
actually clears the CPU's IRQ line.
This register is marked read/write in another doc, with no explanation.
IRQ is cleared on power on or reset.
The '-' bits are open bus.